1. Field of the Invention
The present invention relates generally to methods for forming vias through dielectric layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming self-aligned vias through dielectric layers within microelectronics fabrications.
2. Description of the Related Art
Integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit microelectronics fabrication technology has advanced and integrated circuit microelectronics fabrication device dimensions have decreased, it has become increasingly important within advanced integrated circuit microelectronics fabrications to form through dielectric layers within those advanced integrated circuit microelectronics fabrications vias of minimal cross-sectional dimension and optimal registration. Vias of minimal cross-sectional dimension and optimal registration formed through dielectric layers within advanced integrated circuit microelectronics fabrications are particularly desirable when it is desired or required to form within an advanced integrated circuit microelectronics fabrication a via, such as a contact via or an interconnection via, through a portion of a dielectric layer between a pair of closely spaced integrated circuit structures, such as but not limited to a pair of closely spaced patterned integrated circuit conductor structures.
In order to form within integrated circuit microelectronics fabrications vias of minimal cross-sectional dimension and optimal registration through portions of dielectric layers which are separated by closely spaced integrated circuit structures within those integrated circuit microelectronics fabrications, it has become common in the art of advanced integrated circuit microelectronics fabrication to form vias through self-aligned methods which employ pairs of integrated circuit structures as registration aids in forming the vias. A schematic cross-sectional diagram illustrating an integrated circuit microelectronics fabrication through which such a via is formed is illustrated in FIG. 1.
Shown in FIG. 1 is a substrate 10 having formed thereupon a pair of patterned conductor layers 12a and 12b which is typically formed within an integrated circuit microelectronics fabrication from a polysilicon or a polycide conductor material. Each one of the patterned conductor layers 12a or 12b has formed and aligned thereupon a corresponding patterned conductor cap dielectric layer 14a or 14b. Formed adjoining the pair of patterned conductor stack layers formed of: (1) the patterned conductor layer 12a and the patterned conductor cap dielectric layer 14a; and (2) the patterned conductor layer 12b and the patterned conductor cap dielectric layer 14b, is a series of dielectric spacer layers 16a, 16b, 16c and 16d. There is also shown in FIG. 1 formed upon or over the substrate 10, including the structures which form the pair of patterned conductor stack layers, a pair of patterned pre-metal dielectric (PMD) layers 18a and 18b which are formed from a blanket pre-metal dielectric (PMD) layer while employing a pair of patterned photoresist layers 20a and 20b as a pair of patterned photoresist etch mask layers.
When forming the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, it is common to form the insulator spacer layers 16a, 16b, 16c and 16d from a first silicon oxide dielectric material which is at least slightly different from a second silicon oxide dielectric material which is employed in forming the patterned pre-metal dielectric (PMD) layers 18a and 18b. Thus, given an appropriate choice of etchant for etching a blanket pre-metal dielectric (PMD) layer from which is formed the patterned pre-metal dielectric (PMD) layers 18a and 18b, it is then possible to form within the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 the via defined by the patterned pre-metal dielectric (PMD) layers 18a and 18b with minimal, if any, etching of the dielectric spacer layers 16b and 16c.
While there may typically be formed within the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 the via defined by the patterned pre-metal dielectric layers 18a and 18b without substantially etching the dielectric spacer layers 16b and 16c by employing when forming the dielectric spacer layers 16a, 16b, 16c and 16d the first silicon oxide dielectric material which is different from the second silicon oxide dielectric material which is employed in forming the patterned pre-metal dielectric (PMD) layers 18a and 18b, there nonetheless exists problems in forming within the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 the via self-aligned with the dielectric spacer layers 16b and 16c when the patterned photoresist layers 20a and 20b are substantially mis-aligned with respect to the patterned conductor layers 12a and 12b. A schematic cross-sectional diagram illustrating one of the problems is shown in FIG. 2.
Shown in FIG. 2 is a schematic cross-sectional diagram of an integrated circuit microelectronics fabrication largely equivalent to the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the patterned photoresist layers 20a and 20b have been mis-aligned with respect to the patterned conductor layers 12a and 12b, thus forming the mis-aligned patterned photoresist layers 20a' and 20b'. Similarly, there is also shown in FIG. 2 the mis-aligned patterned pre-metal dielectric (PMD) layers 18a' and 18b' which are formed when employing the mis-aligned patterned photoresist layers 20a' and 20b' as a photoresist etch mask layer. In addition, as is illustrated in FIG. 2, the mis-aligned patterned photoresist layers 20a' and 20b' are sufficiently mis-aligned such that there is also etched: (1) the patterned conductor cap dielectric layer 14a to form an etched patterned conductor cap dielectric layer 14a'; and (2) the dielectric spacer layer 16b to form the etched dielectric spacer layer 16b'.
As is understood by a person skilled in the art, the integrated circuit microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 typically yields functionality and reliability problems in forming a fully functional or reliable integrated circuit microelectronics fabrication. The functionality and reliability problems are encountered when a conductor stud layer is formed into the via defined in part by the mis-aligned patterned pre-metal dielectric (PMD) layers 18a' and 18b', since the reduced thicknesses of the etched patterned conductor cap dielectric layer 14a' and the etched dielectric spacer layer 16b' at the upper edge of the patterned conductor layer 12a are more likely to inadequately insulate the patterned conductor layer 12a from the conductor stud layer.
It is thus towards the goal of forming through portions of dielectric layers between horizontally spaced microelectronic structures within microelectronics fabrications self-aligned vias with optimal cross-sectional profiles even under circumstances where there is mis-aligned patterned photoresist layers employed as etch mask layers in forming those vias that the present invention is generally directed.
Various methods have been disclosed in the art of microelectronics fabrication for etching dielectric layers within microelectronics fabrications.
For example, Dahm et al., in U.S. Pat. No. 5,431,778 discloses a dry etch method for selectively or non-selectively etching silicon containing material layers, such as silicon oxide layers, within integrated circuit microelectronics fabrications. The method employs a fluorine containing source material selected from either hydrogen fluoride or fluorine, and a carbon-oxygen source material selected from either carbon monoxide or carbon dioxide. Through the dry etch method there is avoided the use of atmospheric ozone depleting halocarbon etchant gases which are traditionally employed in etching silicon containing material layers within integrated circuit microelectronics fabrications.
In addition, Mihara et al., in U.S. Pat. No. 5,447,598 discloses a method for forming within an integrated circuit microelectronics fabrication a resist mask pattern employed upon a high step height topography substrate layer within the integrated circuit microelectronics fabrication. The high step height topography substrate layer may include a high step height topography dielectric substrate layer. The method employs a hard mask layer for patterning a planarizing resist layer formed upon the high step height topography substrate layer, where when patterning the planarizing resist layer there is employed along with an oxygen etchant gas a additional gas which forms a protective oxide layer on the sidewalls of a via formed through the planarizing resist layer.
Desirable in the art are additional self-aligned methods through which vias may be formed through portions of dielectric layers between microelectronic structures within microelectronics fabrications with optimal cross-sectional profiles, even under circumstances where there is mis-aligned a patterned photoresist layer employed as an etch mask layer in forming those vias. Particularly desirable in the art are additional self-aligned methods through which vias may be formed through portions of dielectric layers between integrated circuit microelectronic structures within integrated circuit microelectronics fabrications with optimal cross-sectional profiles, even under circumstances where there is mis-aligned a patterned photoresist layer employed as an etch mask layer in forming those vias. It is towards the foregoing goals that the present invention is more specifically directed.